Flat, virtual flat, hierarchical, chip-assembly flows
Advanced STA (MMMC, AOCV, POCV)
Formal LEC
At-Speed Clocking for Transition, Path-Delay and Timing Aware ATPG
Static and Dynamic Power Verification
Physical Verification
Physical Synthesis, Floorplan, Place and Route
DFT Insertion and Verification
ESD and Reliability Analysis
Parasitic Extraction
Multiple Voltage Design
Complex Clocking Schemes: Clock Mesh, Multisource
Test Compression
Analogue and Mixed Signal DfT
BIST, Memory Repair and Standard Scan
IR/EM Analysis
